Project Title: ”Pilot Integration 3nm Semiconductor technology”
Project Type: H2020 European Project
In the PIn3S project, the aim is to realize Pilot Integration of a 3nm Semiconductor Integrated Circuit (IC) process technology, the next node on the roadmap for Logic IC manufacturing. The innovations proposed in this project will ensure that the European semiconductor equipment sector and ecosystem can capitalize on the exponential growth expected in this sector, create sustainable job growth and stay ahead of the curve in terms of worldwide technological leadership.
After the conception of the MOS transistor and the invention of integration of MOS devices and interconnect on a planar substrate in the early 60’s, successive process generations have been generated on a bi-yearly basis in which the gate length of the transistor scaled by 0.7x every generation.
For many years lithography is one of the enabling forces behind the continuous success of shrinking dimensions and thereby enabling technical and economic advances that have been depicted as “Moore’s law”.
The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This entails successful development and integration of process modules to a sufficiently high maturity level, development of adequate patterning technology and metrology capabilities. In addition, PIn3S aims to supplement the EUV Mask infrastructure with the development of Mask Repair Equipment to enable cost effective mask creation for the 3nm node and beyond.
Lithography is the key enabler for continuing the shrink in feature size needed to support Moore’s law. Realization of cost effective High Volume Manufacturing ready Lithography equipment capable to meet the 3nm node Technology requirements for Feature size, Overlay and Productivity is the leading objective for this project. In Lithography the specific objectives can be summarized as follows:
• Optimize EUV based lithography scanners to enable single expose patterning at 3nm node requirements by further development, performance validation and wafer exposures of the EUV Hyper NA scanner prototype with anamorphic optics at an NA of 0.55.
• Enhance cost effective High Volume Manufacturing (HVM) of 3nm node integrated devices by development and realization of a 3nm node capable DUV immersion scanner prototype, containing DUV optics with deformable mirror technology, matched on overlay performance with EUV scanners and meeting the increased productivity requirements. • Development of an advanced Lithography optics prototype using a novel actuation concept for a deformable mirror technology for both DUV immersion as well as EUV lithography scanners to improve the optics overlay budget by a factor of two.