Field Effect Transistors

 

Field Effect Transistors are realized in CSSNT using Electron Beam Lithography (EBL). A highly doped Si substrate is used as Bottom Gate Electrode. The Gate Dielectric is a SiO₂ layer positioned under the Gold Source and Drain Electrodes. The uniqueness of the FETs designed in our lab in represented by the Nano-Objects used in the channels: SWCNTs, MWCNTs, Nanowires, Nanobelts, etc. The first image below shows a Nano-FET Schematics (left) and a FET obtained using an InP Nanowire (right).

 

 

The Nano-FETs Construction is shown in the images below. As it can be seen, after the dispersion on the Nanowires, some can form a direct contact with the existing electrodes, and some need additional electrodes to be constructed using EBL in order to have electrical contact.

 

 

The workflow used in obtaining the additional electrodes is presented below (first image), as schematic and as real images obtained during the workflow.

 

 

The image below shows real micrographs obtained during the workflow of creating the additional electrodes. The first image on the left shows the design of the additional electrodes. The middle images show the pattern obtained after the EBL exposure and the images from the right show the additional electrodes after the Gold deposition in the previously obtained pattern.